VIA

6522 Versatile Interface Adapter

The 6522 VIA controls all input and output of the Oric system excluding the expansion port.

It is memory addressed from locations #0300 to #030F.

LOC	MNE	DESCRIPTION (TABLE1)	As you can see from the table to the left (TABLE1), this single chip houses a powerful array of input /output devices. The VIA handles all interrupts, transfers to or from the Sound chip, Data communication to the Printer Port, Cassette input/output, Keyboard interfacing and soft reset. PORT B is dedicated. This means that each bit has been assigned (cannot change) a specific duty (apart from bit 5). This is shown in Table 2. Port A doubles up as the 8 lines for the Printer port as well as the 8 data lines for the Programmable Sound Generator (AY-3-8912 PSG). Each port has been provided with two sets of handshake lines. CA1 and CA2 for port A and CB1 and CB2 for port B. CA1 and CB1 are input only but may be set to be responsed on negative or positive active edges.
0300	IORB	PORT B
0301	IORA	PORT A (HS)
0302	DDRB	DATA DIRECTION B
0303	DDRA	DATA DIRECTION A
0304	T1CL	TIMER 1 COUNTER LO
0305	T1CH	TIMER 1 COUNTER HI
0306	T1LL	TIMER 1 LATCH LO
0307	T1LH	TIMER 1 LATCH HI
0308	T2CL	TIMER 2 LATCH/CNT
0309	T2CH	TIMER 2 COUNTER
030A	SR	SHIFT REGISTER
030B	ACR	AUXILLARY CONTROL
030C	PCR	PERIPHERAL CONTROL
030D	IER	INTERRUPT ENABLE
030E	IFR	INTERRUPT FLAGS
030F	IORA	PORT A (NO HS)

CB2 and CA2 can both be programmed to act in different ways. Table 3 iterates this. All control over the states of CA1, CA2, CB1 and CB2 are held within the Peripheral Control Register (PCR).

BIT	MNE	DESCRIPTION (TABLE2)	CA2 and CB2 are used to control data transfers to the PSG. CA1 is used for the ACK line on the Printer port. CB1 receives data from the Cassette input. Within the context of the PCR, bit 0 is the only control over CA1. Setting the bit will set a possible interrupt response only on a positive active edge whilst with the bit cleared, the interrupt may only act upon a negative active edge. This is the same for CB1 on BIT4.
0	RW0	BIT 0 OF KEY ROW ADDR.
1	RW1	BIT 1 OF KEY ROW ADDR.
2	RW2	BIT 2 OF KEY ROW ADDR.
3	KS	KEYBOARD RESPONSE
4	STB	PRINTER STROBE
5	-	NOT USED
6	RLY	CASSETTE RELAY
7	CST	CASSETTE OUPUT LINE

Bits 1 to 3 set the state of CA2 whilst the remaining bits from 5 to 7 set the state of CB2.

DEC	BIN	DESCRIPTION (TABLE 3) LOCATION 030C	EFF LOGIC
0	000	INPUT NEGATIVE ACTIVE EDGE	1
1	001	INDEPENDANT INTERRUPT NEGATIVE ACTIVE EDGE (INPUT)	1
2	010	INPUT POSITIVE ACTIVE EDGE	1
3	011	INDEPENDANT INTERRUPT POSITIVE ACTIVE EDGE (INPUT)	1
4	100	HANDSHAKE OUTPUT (ON WRITING TO RELATIVE PORT)	01
5	101	PULSE OUTPUT (ON WRITING TO RELATIVE PORT)	10
6	110	LOW OUTPUT (0)	0
7	111	HIGH OUTPUT (1)	1

CB2 has a dual purpose. It is also the data transmission line for the shift Register.

This section of the VIA is little used since CB2 is used for setting the state of the PSG access. Refer to this link for more information about the shift register and particularly communication to the PSG.

Timer 1 is used for Interrupt timing on the Oric. An interrupt occurs every 10th of a second, allowing the Processor to read the keyboard, flash the cursor and update further timers and counters in page 2.

Bit 7	Bit 6	Description (Table 4)	Timer 1 can act in several different ways. Determined by the contents of the ACR (Bits 6 and 7). This is detailed in Table 4. Port B, bit 7 (Cassette output) may also be affected by the setting of the latter two states. In *1 scenario, PB7 will pulse on every time out.
0	0	TIMED INTERRUPT EACH TIME T1 IS LOADED
0	1	CONTINUOUS INTERRUPTS
1	0	TIMED INTERRUPT EACH TIME T1 IS LOADED *1
1	1	CONTINUOUS INTERRUPTS *2

Since Scenario *2 provides continuous interrupts, a square wave output can be achieved on PB7.

This brings forth an interesting situation. By combining the Cassette output line with the Audio output line, one could attain a four channel Sound Source, although not running alongside BASIC.

This site is still under construction, so the rest of this document will have to wait... sorry...